The presently disclosed technology relates to a variable-resistance memory device employing a storage element connected between first and second common lines to serve as an element having its resistance changing in accordance to a voltage applied to the element and relates to an operation method for operating the variable-resistance memory device.
There is known a variable-resistance memory device employing a storage element in every memory cell of the device. The resistance of the memory element changes because conductive ions are injected into an insulator film or conductive ions are pulled out from the insulator film. Refer to documents such as “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada and H. Narisawa, Technical Digest IEDM 2007, pp. 783-786 (hereinafter referred to as Non-Patent Document 1).
The storage element has a laminated structure provided between two electrodes. The laminated structure includes a layer, which serves as a supplier of the conductive ions, and the insulator film. Every memory cell employs a variable-resistance storage element and an access transistor which are connected to each other in series between a bit line and a plate in such a way that active-matrix driving can be applied to the storage element and the access transistor.
Since every memory cell employed in the variable-resistance memory device as described above includes one access transistor (T) and one variable-resistance resistive element (R) serving as a variable-resistance storage element, the variable-resistance memory device is a kind of 1T1R memory adopting a current-drive method. In general, the memory making use of conductive ions and a memory making use of insulation-layer oxidations as well as insulation-layer reductions are popularly referred to as a ReRAM.
In the ReRAM, a large resistance of the storage element is associated with an operation to write data into the memory cell whereas a small resistance of the storage element is associated with an operation to erase data from the memory cell, and the ReRAM is capable of carrying out the operation to write data into the memory cell as well as the operation to erase data from the memory cell by making use of a pulse having a short duration of the order of nanoseconds. Thus, as an NVM (Non-Volatile Memory) capable of carrying out operations at a high speed, the ReRAM draws attention in the same way as the RAM (Random-Access Memory).
FIG. 1 is a diagram showing a correlation between a conductance and a current in an LRS (low-resistance state) of a ReRAM making use of conductive ions. The conductance is the reciprocal of the low resistance (RLRS).
The horizontal axis of FIG. 1 represents the conductance in the LRS whereas the vertical axis of the same figure represents the magnitude of a set current Iset in a resistance reduction operation also referred to as a set operation in this case.
As is obvious from FIG. 1, the resistance of the storage element changes all but linearly with the set current Iset. Such a characteristic can also be realized as well in a variable-resistance memory such as another ReRAM.
Thus, the ReRAM has a merit that the distribution of the resistance can be narrowed by executing the current control with a high degree of precision and a merit that a multi-value memory can be implemented.
However, if the current control is executed with a low degree of precision, on the other hand, the ReRAM has a demerit that it is difficult to obtain a desired narrow distribution of the resistance. In addition, if the current control is executed with a low degree of precision, the ReRAM also has another demerit that it is difficult to carry a reset operation particularly with an excessive magnitude of the current supplied to the ReRAM or another demerit accompanying an overset which is deterioration of the repetition characteristic. The reset operation is an operation carried out to increase the resistance of the storage element.
As a method for controlling the current of the storage element, there are known a word-line current control method for controlling the current of the storage element and a bit-line current control method for controlling a current flowing through a bit line. The word-line current control method is a method for controlling an electric potential appearing at the gate electrode of the access transistor.
In the case of the word-line current control method, the word line includes a number of large gate capacitances as parasitic capacitances due to the fact that the word line is made from metal of the gate electrode. Thus, the wire capacitance is large so that it is difficult to execute the word-line current control method. In the case of the bit-line current control method, on the other hand, the bit line is created on an upper-layer wiring layer. Thus, the wire capacitance per unit length can be reduced. As a result, the word-line current control can be executed by making use of a circuit having a small driving power.
The bit-line current control method for controlling the current of the storage element by controlling a current flowing through the bit line is proper for a cell array structure allowing voltage driving to be carried out by separating not only the bit and word lines, but also source lines in the row or column direction. This current control method can be applied with ease to the so-called 3-line system which is the name of a structure or a system (or, strictly speaking, an access system). Typical examples of the 3-line system are given in “A 5 ns Fast Write Multi-Level Non-Volatile 1 Kbits RRAM Memory with Advance Write Scheme,” Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Tai-Yuan Wu, Frederick T. Chen, Yu-Sheng Chen, Keng-Li Su, Ming-Jer Kao, Kuo-Hsing Cheng and Ming-Jinn Tsai.
With regard to the bit-line current control method applied to the 3-line system, inventors of the presently disclosed technology have already made some proposals described in documents such as Japanese Patent Laid-open No. 2010-170617 (hereinafter referred to as Patent Document 1). In addition, Public-Reannounced Patent No. WO 2007/015358 given below discloses a typical example in which the bit-line current control method is applied to a variable-resistance memory adopting a spin injection system.
In the bit-line current control method applied to the 3-line system as described in Patent Document 1, for example, the drain electrode of an NMOS transistor serving as a current control transistor is connected to the bit line whereas the voltage appearing at the gate electrode of the transistor is controlled by a control circuit. In this control, after an inversion to a resistance reduction state of the storage element, the control circuit controls the current control transistor in order to drive an access transistor to operate in a saturated region and to control an electric potential appearing on the bit line so that a current flowing through the storage element is sustained at a constant magnitude. Thus, even if the resistance of the storage element changes or even if there are variations from storage element to storage element, the set current which is the current flowing through the storage element after the inversion is sustained at a constant magnitude so that it is possible to effectively avoid or repress element-characteristic deteriorations accompanying an overset because no excessive current flows.
As described above, in the 3-line system adopting the bit-line current control method, a resistance changing operation can be carried out at a high speed so that it is possible to repress variations of the resistance distribution obtained after the change of the resistance of the storage element without deteriorating the characteristic of the storage element. In addition, the 3-line system adopting the bit-line current control method offers the merit of a low cost because the size of an area occupied by the control circuit is small due to the fact that it is sufficient to provide even a driving capability lower than that of a system adopting the word-line current control method.
It is to be noted that Non-Patent Document 1 discloses an array configuration in which, because of easiness of a fabrication process, an upper electrode is fabricated into a plate shape and the drain electrode of the access transistor is used as a storage node. In addition, the source electrode of the access transistor is connected to a bit line fabricated into a line shape. Since two lines are used to select a memory cell, the array configuration is referred to as a 3-line system.